# Dissertation: Dissertation: 17.6. Phase-locked loops with active proportionally-integrating filter: the lock-in range computation (Aleksandrov)

17.6.2016 10:00 — 13:00

Location: Mattilanniemi, Agora, Alfa

M.Sc. **Konstantin Aleksandrov** defends his doctoral dissertation in Mathematical Information Technology "Phase-locked loops with active proportionally-integrating filter: the lock-in range computation". Opponent Professor **Sergey Abramovich** (The State University of New York, USA) and custos Professor **Nikolay Kuznetsov** (University of Jyväskylä). The doctoral dissertation is held in English.

The thesis studies phase-locked loops (PLLs) and the related problem of lock-in range computation. The operational principle of PLL is to adjust the phase of local (tunable) oscillator to the phase of a reference oscillator. Nowadays, various PLL modifications are used in radio systems (for example AM/FM radio and software-defined radio), telecommunication systems (for example GSM and CDMA), global positioning systems (GPS), and computer architectures, to name a few. The PLL is an active research area due to the increasing range of possible applications, for example optical PLLs, neuronal PLLs, and others.

The lock-in concept, introduced by IEEE Fellow F.M. Gardner in the 1960's, is used to describe the fast synchronization of oscillators. However in 1979 F.M. Gardner remarked in his book “Phaselock Techniques”, that the suggested definition of the lock-in range may lack rigor in a general case. Still, the lock-in range is a useful concept and it is used in many PLL applications.

In this thesis, the lock-in range of a nonlinear PLL model is studied according to a recently suggested mathematical definition. The nonlinear PLL model is considered with an active proportionally-integrating (PI) filter in the signal's phase space. The derived estimates improve the known estimates of the lock-in range of PLL with an active PI filter. Furthermore, for the case, which is important for applications, the exact value of the lock-in range is derived. Numerical simulations are performed to validate the derived estimates.

**Further information:**

Konstantin Aleksandrov, konstantin.239.alexandrov@gmail.com

University communications, tiedotus@jyu.fi, tel. +358408053638

The dissertation is published in the series Jyväskylä studies in computing number 239, 38 p. (+included articles), Jyväskylä 2016, ISBN 978-951-39-6687-4 (nid.) ISBN 978-951-39-6688-1 (PDF). Available online: http://urn.fi/URN:ISBN:978-951-39-6688-1

Abstract

The present work is devoted to the study of the lock-in range of phase-locked loop (PLL). The PLL concept was originally described by H. de Bellescize in 1932. Nowadays various modifications of PLL are widely used in radio systems (e.g., AM/FM radio, software-defined radio), telecommunication systems (e.g., GSM, CDMA), global positioning systems (GPS), computer architectures, and other domains. PLL is of great current interest due to continued increase of its possible applications (optical PLLs, neuronal PLLs, and others). PLL operating principle is to adjust the phase of a local (tunable) oscillator to the phase of a reference oscillator. The lock-in range concept, which was introduced in 1960’s by IEEE Fellow F. M. Gardner, is used to describe fast synchronization of oscillators without cycle-slipping – the undesired growth of phase

difference. However, in the second edition of the fundamental handbook “Phaselock Techniques”, which was published in 1979, F. M. Gardner remarked that the suggested definition of the lock-in range may lack rigor in general case. Despite this fact, the lock-in range is a useful concept and is used in many PLL applications. Thus, the problem of rigorous lock-in range definition, which was stated

in 1979 by F. M. Gardner, and the lock-in range computation according to its rigorous definition have important applied relevance.

In the present work, the lock-in range of nonlinear PLL model is studied according to a recently suggested rigorous mathematical definition. We pay our attention to the nonlinear PLL model with active proportionally-integrating (PI) filter in the signal’s phase space. The relation for the lock-in range computation is presented. For the case of sinusoidal characteristics of phase detector the analytical estimates of the lock-in range are derived. The estimates we have obtained improve the known estimates of the lock-in range of PLL with active PI filter. For the case of triangular characteristics of phase detector the exact formulae of the lock-in range are obtained. The numerical simulations performed are to confirm the adequacy of the obtained results.

Keywords: phase-locked loop, signal’s phase space, active PI, lock-in range, cycle slipping